This invention pertains to semiconductor processing techniques and more particularly to process techniques utilizing photo-definable layers to create desired structures for semiconductor devices.
The use of organic photoresist polymers as photo-definable mask layers in photolithography processes for the manufacture of semiconductor devices is well known. Typically, organic photoresist materials are used to form temporary surfaces that are removed after desired patterns have been transferred to a semiconductor substrate. The steps utilized to transfer a pattern to the semiconductor substrate often include coating a semiconductor wafer with a liquid organic photoresist layer, exposing the photoresist layer to a light source in a patterned manner, developing the photoresist layer with a liquid developer solution to remove unwanted portions of the photoresist layer, utilizing the remaining portions of the photoresist as an etch mask, and removing these remaining portions of the photoresist after the etch is completed.
It has been previously contemplated to utilize dry processing techniques for forming photo-definable layers to replace the liquid coating and developing steps used for traditional organic photoresists. Example materials that have been proposed for such dry processing techniques are organosilicon resists, such as plasma polymerized methylsilane (PPMS). Techniques for using PPMS as a photo-definable layer has been described in the following articles: Joubert et al., Journal of Vacuum Science Technology, B 12(6), pages 3909-3913 (Nov/Dec 1994); Weidman et al., Applied Phys. Lett., 62(4), pages 372-374 (Jan. 25, 1993); Joshi et al., SPIE, Volume 1925, pages 709-720 (Jan. 1993); Joubert et al., SPIE, Volume 2195, pages 358-371 (1994); Weidman et al., SPIE, Volume 2438, pages 496-512 (1995). With the techniques disclosed, a PPMS layer is deposited through a plasma reaction and exposed to deep ultraviolet (DUV) light in a patterned manner to convert the exposed regions of PPMS to a photo-oxidized siloxane called PPMSO. Next, the non-exposed PPMS portions may be removed, for example with a chlorine plasma etch, leaving the PPMSO portions as a hard mask layer for further processing.
The present invention provides novel and advantageous process techniques for using photo-definable layers in the manufacture of semiconductor devices, including the manufacture of dynamic random access memories (DRAMs), static RAMs (SRAMs), synchronous DRAMs (SDRAMs), FLASH memories, and other memory devices. In particular, the present invention contemplates the use of a photo-definable layer that may be converted into a insulative material and that may remain on a semiconductor structure as an integral component of that structure after the photolithography and etching process steps are completed. The invention, therefore, may serve to reduce the number of processing steps ordinarily required in a given operation due to use of the photo-definable layer.
In one embodiment, the present invention is a process for using a photo-definable layer in a negative mask scheme to manufacture a semiconductor device. This process may include forming a photo-definable layer that is convertible to an insulative material, exposing selected portions of the photo-definable layer to electromagnetic radiation in a negative pattern scheme to convert the selected portions to an insulative material, removing exposed portions of the photo-definable layer, and using the non-exposed portions of the photo-definable layer as a patterned mask for further processing steps. In a further embodiment, the present invention is a semiconductor device including a substrate and at least one feature formed on the substrate by converting selected portions of a photo-definable layer to an insulative material through exposure to electromagnetic radiation in a negative mask scheme and by using non-exposed portions of the photo-definable layer as a mask to form the one feature.
In another embodiment, the present invention is a process for etching an insulative layer using a photo-definable layer in a negative mask scheme. This process may include forming a photo-definable layer that is convertible to an insulative material, exposing selected portions of the photo-definable layer to electro-magnetic radiation in a negative pattern scheme to convert the selected portions to an insulative material, and removing exposed portions of the photo-definable layer and underlying portions of an insulative layer with a single-step etch process. In a further embodiment, the present invention is a patterned insulative structure within a semiconductor device including a substrate and a patterned insulative layer formed on the substrate by converting selected portions of a photo-definable layer to an insulative material through exposure to electro-magnetic radiation in a negative mask scheme and by using non-exposed portions of the photo-definable layer as a mask to form the patterned insulative layer.
In another embodiment, the present invention is a process for etching an insulative layer followed by a conductive layer in the manufacture of a semiconductor device. This process may include forming an insulative layer over a conductive layer on a substrate, forming a photo-definable layer that is convertible to an insulative material, exposing selected portions of the photo-definable layer to electromagnetic radiation to convert the selected portions to an insulative material, removing exposed portions of the photo-definable layer and underlying portions of the insulative layer with a single-step etch process to form a void within the insulative layer, and removing a portion of the conductive layer within the void. In further embodiment, the present invention is a conductive interconnect structure within a semiconductor device including a substrate, a first conductive layer over the substrate, and an insulative layer over the conductive layer. This structure may further include a second conductive layer formed within a desired portion of the insulative layer to create a conductive interconnect structure connected to the first conductive layer. This second conductive layer may be formed by converting selected portions of a photo-definable layer to an insulative material through exposure to electromagnetic radiation in a negative mask scheme, by using non-exposed portions of the photo-definable layer as a mask to form a pattern within the insulative layer, and by using non-exposed portions of the photo-definable layer as a sacrificial mask in etching the second conductive layer.
In yet another embodiment, the present invention is a process for using a photo-definable layer to underlie an organic photoresist layer during the manufacture of an integrated circuit structure is provided. This process may include forming a photo-definable layer that is convertible to an insulative material, creating a patterned organic photoresist layer over the photo-definable layer to leave unmasked portions of the photo-definable layer, exposing selected portions of the photo-definable layer to electromagnetic radiation to convert the selected portions to an insulative material, and removing exposed portions of the photo-definable layer and underlying portions of the insulative layer with an etch process to form a void within the insulative layer. In a further embodiment, the present invention is a patterned insulative structure including a substrate and an insulative layer on the substrate formed by covering a photo-definable layer with a patterned organic photoresist, by converting unmasked portions of a photo-definable layer to an insulative material through exposure to electromagnetic radiation in a negative mask scheme, and by using non-exposed portions of the photo-definable layer and the organic photoresist as a mask to form a pattern within the insulative layer.
In a still further embodiment, the present invention is a process for using a photo-definable layer including forming a photo-definable layer that is convertible to an insulative material, exposing selected portions of said photo-definable layer to electromagnetic radiation in a positive pattern scheme to convert the selected portions to an insulative material, removing non-exposed portions of the photo-definable layer with an etch process, using the non-exposed portions of the photo-definable layer as a patterned mask for further processing steps, and leaving the exposed portions of the photo-definable layer as an insulative layer within the device. In a further embodiment, the present invention is a semiconductor device including a substrate and at least one feature formed on the substrate by converting selected portions of a photo-definable layer to an insulative material through exposure to electromagnetic radiation in a negative mask scheme, by using exposed portions of the photo-definable layer as a mask to form at least one feature, and by leaving the exposed portions of the photo-definable layer on the substrate as an insulative layer.
In another embodiment, the present invention is a process for forming a self-aligned contact during the manufacture of a semiconductor device using a photo-definable layer in a positive mask scheme. This process may include forming an insulative layer over a substrate having at least two spaced structures, forming over the insulative layer a photo-definable layer that is convertible to an insulative material, exposing selected portions of the photo-definable layer to electromagnetic radiation in a positive pattern scheme to convert the selected portions to an insulative material, and removing non-exposed portions of the photo-definable layer with an etch process to expose selected portions of the insulative layer between the spaced structures. The process may also include removing the selected portions of the insulative layer to expose underlying portions of the substrate and depositing conductive material to form a self-aligned contact between the spaced structures. In a further embodiment, the present invention may be a self-aligned contact structure within a semiconductor device formed using a photo-definable layer in a positive mask scheme. This structure may include a substrate, an insulative layer formed on the substrate, and at least one self-aligned contact formed on the substrate by converting selected portions of a photo-definable layer to an insulative material through exposure to electromagnetic radiation in a positive mask scheme and by using exposed portions of the photo-definable layer as a mask to form at least one self-aligned contact.
In yet a further embodiment, the present invention is a process for using a photo-definable layer in a Damascene process to create a patterned structure. This process may include forming a photo-definable layer that is convertible to an insulative material, exposing selected portions of the photo-definable layer to electromagnetic radiation to convert the selected portions to an insulative material, removing non-exposed portions of the photo-definable layer with an etch process to form a desired pattern within the exposed portions of the photo-definable layer, and leaving the exposed portions of the photo-definable layer on the substrate as an insulative layer. In a further embodiment, the present invention is a conductive interconnect structure including a substrate, and a patterned insulative layer on the substrate formed by converting selected portions of a photo-definable layer to an insulative material through exposure to electromagnetic radiation in a positive mask scheme, by removing non-exposed portions of the photo-definable layer to form a pattern within the photo-definable layer, and by leaving the exposed portions of the photo-definable layer as the patterned insulative layer. Additionally, this structure may include a conductive layer inlaid within the patterned insulative layer.
In another embodiment, the present invention is a process for using a photo-definable layer in a dual Damascene process to create a patterned structure. This process may include forming a first photo-definable layer that is convertible to an insulative material and exposing selected portions of the first photo-definable layer to electromagnetic radiation to convert the selected portions to an insulative material to define desired contact areas. The process may also include forming a second photo-definable layer that is convertible to an insulative material, exposing selected portions of the second photo-definable layer to electromagnetic radiation to convert the selected portions to an insulative material to define a desired interconnect pattern, and removing non-exposed portions of the first and second photo-definable layers to form voids exposing the desired contact areas and the desired interconnect pattern. In a further embodiment, the present invention is a conductive interconnect structure including a substrate, a first conductive layer on the substrate, and a patterned insulative layer on the first conductive layer formed by converting selected portions of a photo-definable layer to an insulative material through exposure to electromagnetic radiation in a positive mask scheme, by removing non-exposed portions of the photo-definable layer to form a pattern within the photo-definable layer, and by leaving the exposed portions of the photo-definable layer as the patterned insulative layer. This structure may further include a second conductive layer inlaid within the insulative layer forming contacts with selected portions of the first conductive layer.